1. Field of the Invention
The present invention relates to a data driver of a display device, a test method and a probe card for the data driver and, more particularly, to a technique suitable for testing a repair amplifier of a data driver.
2. Description of Related Art
Flat panel displays become widely used in recent years. There are various types of flat display panels such as the TFT (abbreviating “a Thin Film Transistor”) type liquid crystal display device, the simple matrix type liquid crystal display device, the electroluminescence (abbreviated as “EL”) display device and the plasma display device. On a display (i.e., a screen) of the display device, display data are displayed. In the following, the TFT type liquid crystal display is used as an example for explanation.
FIG. 1 illustrates a configuration of a TFT type liquid crystal display device 1.
The TFT type liquid crystal display device 1 is provided with a glass substrate 3, a display part (i.e., a liquid crystal panel) 10, first to m-th m gate lines G1 to Gm and first to n-th n data lines D1 to Dn. The liquid crystal panel 10 has a plurality of pixels 11 arranged in a matrix on the glass substrate 3. For example, (m×n) numbers of pixels 11 are arranged on the glass substrate 3 (here, m and n each are an integer of 2 or more indicating the numbers of the rows and the columns of the matrix, respectively). Each of the m×n pixels 11 includes a thin film transistor (abbreviated as a “TFT”) 12 and a pixel capacitor 15. The pixel capacitor 15 includes a pixel electrode and an opposite electrode disposed opposite to the pixel electrode. The TFT 12 is provided with a drain electrode 13, a source electrode 14 connected to the pixel electrode and a gate electrode 16. Each of the m gate lines G1 to Gm is connected to the gate electrode 16 of the TFT 12 in the pixel 11 in the m-th row. Each of the n data lines D1 to Dn is connected to the drain electrode 13 of the TFT 12 in the n-th pixel 11 in the n-th column.
The TFT type liquid crystal display device 1 is further provided with a gate driver 20 and a data driver 30. The gate driver 20 is mounted on a chip, not illustrated, and is connected to one end of each of the m gate lines G1 to Gm. In the meantime, the data driver 30 is mounted on the chip, and is connected to one end of each of the n data lines D1 to Dn.
The TFT type liquid crystal display device 1 is still further provided with a timing controller 2. The timing controller 2 supplies a gate clock signal GCLK for use in selecting a gate line G1 in, for example, one horizontal period of time to the gate driver 20. The gate driver 20 outputs a selection signal to the gate line G1 in response to the gate clock signal GCLK. At this time, the selection signal is transmitted to the gate line G1 from one end to the other end in this order, and then, the TFTs 12 of the (1×n) pixels 11 corresponding to the gate line G1 are turned on in response to the selection signal supplied to the gate electrode 16.
Moreover, the timing controller 2 supplies a clock signal CLK and one line display data DATA for the display of one line to the data driver 30. The one line display data DATA includes n pieces of display data corresponding to the data lines D1 to Dn respectively. The data driver 30 outputs the n pieces of display data to the n data lines D1 to Dn, respectively, in response to the clock signal CLK. At this time, the TFTs 12 of the (1×n) pixels 11 corresponding to the gate line G1 and the n data lines D1 to Dn are turned on. As a consequence, the n pieces of display data are written in the pixel capacitors 15 in the (1×n) pixels 11, respectively, to be stored till next writing. In this manner, the n pieces of display data are displayed as the one line display data DATA.
FIG. 2 illustrates a configuration of the data driver 30. The data driver 30 is cascaded in a columnar direction from first to x-th in this order. Here, x is an integer of 2 or more.
The data driver 30 is provided with a shift register 31, a data register 32, a latch circuit 33, a level shifter 34, a DAC (abbreviating “a Digital to Analog Converter) 35, an amplifier circuit 36 and a gray-scale voltage generation circuit 37.
The gray-scale voltage generation circuit 37 includes a plurality of gray-scale correction resistor elements, not illustrated, connected in series. The gray-scale voltage generation circuit 37 divides a reference voltage supplied from a power source circuit, not illustrated, into a plurality of gray-scale voltages by the plurality of gray-scale correction resistor elements. For example, in a case where an image is displayed with a 64-level gray-scale in the TFT type liquid crystal display device 1, the gray-scale voltage generation circuit 37 divides reference voltages V0 to V7 into positive gray-scale voltages with the 64-level gray-scale as the plurality of gray-scale voltages by 63 gray-scale correction resistor elements R0 to R62. The same goes for negative gray-scale voltages.
The shift register 31 includes n shift registers, not illustrated. The data register 32 includes n data registers, not illustrated. The latch circuit 33 includes n latch circuits, not illustrated. The level shifter 34 includes n level shifters, not illustrated.
The DAC 35 includes n DACs (see FIG. 3). The n DACs each include a P type converter PchDAC for outputting the positive gray-scale voltage as an output gray-scale voltage and an N type converter NchDAC for outputting the negative gray-scale voltage as another output gray-scale voltage. For example, odd-numbered DACs out of the n DACs are assumed to be PchDACs whereas even-numbered DACs are assumed to be NchDACs. The DAC 35 further includes n switch elements for reversely driving, that is, output switching by alternately applying the positive gray-scale voltage and the negative gray-scale voltage to the pixel 11 (see FIG. 3). The amplifier circuit 36 includes n amplifiers 36-1 to 36-n (see FIGS. 2 and 3).
Next, an operation of the TFT type liquid crystal display device 1 will be described below.
For example, the timing controller 2 supplies the clock signal CLK and the one line display data DATA to the x data drivers 30, and further, supplies a shift pulse signal STH to the first data driver 30. Each of the x data drivers 30 outputs the n pieces of display data included in the one line display data DATA to the n data lines D1 to Dn, respectively, in response to the clock signal CLK and the shift pulse signal STH.
In the i-th (here, i=1, 2, . . . and x−1) data driver 30, the n shift registers in the shift register 31 sequentially shift the shift pulse signal STH in synchronization with the clock signal CLK, and then, outputs it to the n data registers in the data register 32. The n-th shift register in the shift register 31 outputs the shift pulse signal STH to the n-th data register in the data register 32, and further, outputs it to an (i+1)th (here, i=1, 2, . . . and x−1) data driver 30 (i.e., cascade-output). In the x-th data driver 30, the n shift registers in the shift register 31 sequentially shift the shift pulse signal STH in synchronization with the clock signal CLK, and then, outputs it to the n data registers in the data register 32.
In each of the x data drivers 30, the n data registers in the data register 32 get the n pieces of display data supplied from the timing controller 2 in synchronization with the shift pulse signals STH outputted from the n shift registers in the shift register 31, respectively, and then, output them to the latch circuit 33. The n latch circuits in the latch circuit 33 latch the n pieces of display data supplied from the n data registers in the data register 32 at the same timing, respectively, and then, output them to the level shifter 34. The n level shifters in the level shifter 34 subject the n pieces of display data to level shifting, respectively, and then, output them to the DAC 35. In the DAC 35, the n DACs perform digital/analog-conversion of the n pieces of display data supplied from the n level shifters in the level shifter 34, respectively, and then, the n switch elements switch the outputs.
As illustrated in FIG. 3, for example, the odd-numbered (first, third, . . . and (n−1)th) PchDACs select, from the positive gray-scale voltages with the 64-level gray-scale, output gray-scale voltages in accordance with the pieces of display data outputted from the odd-numbered (first, third, . . . and (n−1)th) level shifters, and then, output them to the odd-numbered amplifiers 36-1, 36-3, . . . and 36-(n−1) in the amplifier circuit 36 via the odd-numbered (first, third, . . . and (n−1)th) switching elements, respectively. In this case, the even-numbered (second, fourth, . . . and n-th) NchDACs select, from the negative gray-scale voltages with the 64-level gray-scale, output gray-scale voltages in accordance with the pieces of display data outputted from the even-numbered (second, fourth, . . . and n-th) level shifters, and then, output them to the even-numbered amplifiers 36-2, 36-4, . . . and 36-n in the amplifier circuit 36 via the even-numbered (second, fourth, . . . and n-th) switching elements, respectively.
In contrast, in a case of the reverse driving, as illustrated in FIG. 3, the odd-numbered (first, third, . . . and (n−1)th) PchDACs select, from the positive gray-scale voltages with the 64-level gray-scale, output gray-scale voltages in accordance with the pieces of display data outputted from the odd-numbered (first, third, . . . and (n−1)th) level shifters, and then, output them to the even-numbered amplifiers 36-2, 36-4, . . . and 36-n in the amplifier circuit 36 via the odd-numbered (first, third, . . . and (n−1)th) switching elements, respectively. In this case, the even-numbered (second, fourth, . . . and n-th) NchDACs select, from the negative gray-scale voltages with the 64-level gray-scale, output gray-scale voltages in accordance with the pieces of display data outputted from the even-numbered (second, fourth, . . . and n-th) level shifters, and then, output them to the odd-numbered amplifiers 36-1, 36-3, . . . and 36-(n−1) in the amplifier circuit 36 via the even-numbered (second, fourth, . . . and n-th) switching elements, respectively.
As a consequence, the DAC 35 outputs, to the amplifier circuit 36, the n output gray-scale voltages subjected to the digital/analog conversion and the output switching over. The n amplifiers 36-1 to 36-n in the amplifier circuit 36 input the n output gray-scale voltages, respectively, and then, output them to the n data lines D1 to Dn.
For the display panel (exemplified by the liquid crystal panel 10) as described above, high precision is required, so that the width of the signal line such as the gate lines G1 to Gm and the data lines D1 to Dn has been reduced. As a result, the possibility of breakage caused by foreign matters in a fabricating process or deficiency in a lithographic process bas been becoming high. If a signal line is broken when the driver outputs the drive signal for driving the signal line, the pixels arranged forward of the broken portion cannot be driven. For example, it is assumed that a driver is represented by the above-described data driver 30, and the signal lines are represented by the above-described data lines D1 to Dn, the drive signal is represented by the above-described n output gray-scale voltages (i.e., the n pieces of display data) and a data line Dj (here, j is an integer satisfying an expression: 1≦j≦n) is broken, the pixels 11 arranged forward of the broken portion cannot be driven. In this case, the display device results in a defective device. One can find this deficiency only when an electric test is conducted at the final stage at which the panel is fabricated and the driver, the substrate and the like are connected and assembled, so that a vast cost occurs when a deficiency is found out.
To tackle the problem, in the technique disclosed in Japanese Laid-Open Patent Application JP-A-Heisei, 8-171081, a repair circuit (also referred to as a rescue circuit) is disposed in a driver in advance, so that pixels arranged forward of a broken portion are driven via the repair circuit when a breakage is found. In the following, this technique will be simply explained by using the example of the TFT type liquid crystal display device 1 described above.
As illustrated in FIG. 4, the data driver 30 in the TFT type liquid crystal display device 1 is further provided with a repair amplifier 40. The repair amplifier 40 is illustrated independently of the data driver 30 for the sake of convenience of explanation. The repair amplifier 40 is mounted on a chip, and includes, for example, two repair amplifiers 40-1 and 40-2. The TFT type liquid crystal display device 1 is further provided with auxiliary interconnections 41 and 42 mounted on the glass substrate 3.
In the case where breaking 43 is found on a data line Dj, a part of the data line Dj still connected to the amplifier 36-j, which is represented by Dj′ (referred to as a connected data line), and the auxiliary interconnection 41 are connected at their intersectional position. Moreover, the auxiliary interconnection 41 is connected to an input of the repair amplifier 40-1 at their intersectional position 45. Additionally, an output of the repair amplifier 40-1 is connected to the auxiliary interconnection 42 at their intersectional position 46. Furthermore, the auxiliary interconnection 42 is connected to a part of the data line Dj not connected to the amplifier 36-j, which is represented by Dj″ (referred to as a disconnected data line) at their intersectional position 47. Consequently, a repair circuit is constructed of a channel consisting of an output of the amplifier 36-j, the connected data line Dj′, the intersection 44, the auxiliary interconnection 41, the intersection 45, the repair amplifier 40-1, the intersection 46, the auxiliary interconnection 42, the intersection 47 and the not-connected data line Dj″. Through the repair circuit, the pixels 11 arranged forward of the breaking 43 can be driven. Here, the repair amplifier 40-1 is used for compensating the decrease of driving performance due to a resistance of the repair circuit.
During an electric characteristics inspection of a display driver IC having the repair circuit, an electric characteristics inspection for the repair amplifiers 40-1 and 40-2 is also conducted in addition to other electric characteristics inspections.
As illustrated in FIG. 5, the data driver 30 in the TFT type liquid crystal display device 1 is further provided with a pad for conducting the electric characteristics inspections. The pad is mounted on the chip.
The pad includes output pads 56-1 to 56-n, repairing input pads 51-1 and 51-2 and repairing output pads 52-1 and 52-2. The output pads 56-1 to 56-n are connected to outputs of the n amplifiers 36-1 to 36-n in the amplifier circuit 36, respectively. The repairing input pads 51-1 and 51-2 are connected to inputs of the repair amplifiers 40-1 and 40-2, respectively. The repairing output pads 52-1 and 52-2 are connected to outputs of the repair amplifiers 40-1 and 40-2, respectively.
At the time of an electric characteristics inspection, a measurement equipment 53 is connected to the chip. The measurement equipment 53 includes a probe card 54 and a tester 55. As the tester 55, a mass-produced LSI tester can be used.
For example, at the time of an electric characteristics inspection, the measurement equipment 53 tests an output delay of each of the n amplifiers 36-1 to 36-n in the amplifier circuit 36. In this case, the probe card 54 inputs drive signals (i.e. the output gray-scale voltages) supplied to the output pads 56-1 to 56-n via the n amplifiers 36-1 to 36-n by the output switch by the DAC 35, and then, outputs the drive signals to the tester 55. The tester 55 tests the output delay of each of the n amplifiers 36-1 to 36-n based on the drive signals, and then, determines the quality based on the output delay time representing the output delay. The quality is determined based on whether or not the output delay time is over a predetermined upper limit. For example, when the output delay time is below the upper limit, the result shows it is a good product: in contrast, when the output delay time is over the upper limit, the result shows it is a deficient product.
Moreover, as one of the electric characteristics inspections, the measurement equipment 53 tests an output delay of each of the repair amplifiers 40-1 and 40-2. In this case, the tester 55 supplies signals to the repairing input pads 51-1 and 51-2. The probe card 54 receives signals supplied to the repairing output pads 52-1 and 52-2 via the repair amplifiers 40-1 and 40-2, and then, outputs the signals to the tester 55. The tester 55 tests output delays of the repair amplifiers 40-1 and 40-2 based on the signals, respectively, and then, determines the quality based on the output delay time representing the output delay.